Large scale multi-level information processing system employing improved failsaft techniques

ABSTRACT

A multiprogrammed multiprocessing information processing system having independently operating computing, input/output, and memory modules through an exchange, and interacting with a multilevel operating system designed to automatically makes optimum use of all system resources by controlling system resources and by scheduling jobs in the multiprogramming mix of the processing system. In operation, the operating system insures that all system resources are automatically allocated to meet the needs of the programs introduced into the system as well as insuring the continuous and automatic reassignment of resources, the initiation of new jobs, and the monitoring of their performance. System reliability is achieved by the incorporation of error detection circuit throughout the system, by single-bit correction of errors in memory, by recording errors for software analysis and by modularization and redundacy of critical elements.

United States Patent 1191 Perpiglia 1 1 Sept. 9, 1975 [75] Inventor: Frank Joseph Perpiglia, Springfield,

[73] Assignee: Burroughs Corporation, Detroit,

Mich.

[22] Filed: Aug. 15, 1973 [21] Appl. No.: 388,551

R27,703 7/l973 Stafford et al. 34O/l7215 Primary ExaminerGareth D. Shaw Assistant ExaminerMark Edward Nusbaum Anomey, Agent, or FirmEdmund M. Chung; Edward J. Feeney, Jrs, Kevin R. Peterson ABSTRACT A multiprogrammed multiprocessing information processing system having independently operating computing, input/output, and memory modules through an exchange, and interacting with a multi-level operating system designed to automatically makes optimum use [52] 340M725; 235/153 AK of all system resources by controlling system resources [511 f 11/06; G06f 5/16 and by scheduling jobs in the multiprogramming mix [58] Field of Search 340/1725; 235/l53 AK of the processing system In operation, the operating system insures that all system resources are automati- [561 Reerences Cited cally allocated to meet the needs of the programs in- UNITED STATES PATENTS troduced into the system as well as insuring the con- 3 266.020 8/1966 Cheney et a1 340/1725 tinuous and automatic reassignment of resources, the 3,3l 5/1967 n 6! a1 i .1 340/1725 initiation of new jobs, and the monitoring of their per- J 12/1968 Marx 4 340/1725 formance. System reliability is achieved by the incor- 3548382 12/1970 Llcmy 340/1725 poration of error detection circuit throughout the sys- 3,566,357 2/l97l Ling 340/1725 single bit correction of errors in y, y l 11,197 Baynard et 340/1725 recording errors for software analysis and by modular- 3,760,365 9/1972 Kurtzberg et al. 340/1725 3.737.816 1/1974 Hauck et al. .1 340 1725 and redundacy of meal elements 3,787,8l8 H1974 Arnold et al 340/1725 1792,4421 2/1974 Bennett et al. 340/1725 2 Clams 55 Drawmg F'gures HENRY MODULES LEGEND CPM- CENTRAL PROCESSOR MODULE IUM= INPUT/OUTPUT MODULE MDU= MAINTENANCE DIAGNOSTIC UNll' PATENTED SEP 9 I975 MEMORY MODULES LECEND CPM CENTRAL PROCESSOR MODULE IOM INPUT/OUTPUT MODULE MDU= MAINTENANCE DIAGNOSTIC UNIT PATENT'EDSEP SL975 3. 905.023

Fig.2 FIGZA FIGZB T 6 1 DATA DATA COMMUNICATIONS COMMUNICATIONS PPDDEssDR PROCESSOR l |\/79-SCANBUS 40 EX Ex 1 T I m EUI DFC EUI DFC 4 2 DEC 4 DFO DH) rm DFC DED DFC DEPDD m0 DFPCC EH20 DEPcc Ex DFPCG Ex UFO EUI DFC EDT 4 z 4 DFO DFC x DTD DFC x DH) 20 DH) 20 DED \EUBO DFC ED2D T 'Y9-SCANBUS DATA DATA COMMUNICATIONS COMMUNICATIONS PROCESSOR PROCESSOR l 36 J LEGEND MSU MEMORY STORAGE UNIT MCM MEMORY CONTROL MODULE PC PERIPHERAL CONTROL PDD PERIPHERAL DDATRDL CABINET DFO= DISK FILE OPTIMIZER i9 DFC DISK FILE CONTROL DF PCC=D|SK FILE PERIPHERAL CONTROL DADTAET Eu ELECTRONICS UNIT Ex EXCHANGE PATENTEUSEP 9i975 39051023 SHEE' UOR2T MATMTEMAMOE 55 DTAOMOsTTO /26 UNIT I /56\ I 32-MAINTENANCE DATA DATA MEMORY M DULE BUS OOMMUMLOATTOMs OOMMUMTOATTOMs Mgu MSU M51] gu 0 PROCESSOR PROCESSOR 300 OOTTAMA m I l MCMO MODULE MEMORY M DULE P60 P06 MSUMSU|MSU M511 :sPc 5P0: :sPO 5P0: 50th DOR UA MGM OEMTRAL 4 PRDOEssOR 5 MODU E CENTRAL PROCESSOR 58 MODULE MsU MSU MSU MSU 5 P00 FCC (2ORAMA McMT MODULE I/ T DATA DATA 4? MEMORYBUS COMMUNlCATIONS COMMUNICATIONS O PROCESSOR PROCESSOR LMTEARUPT BUS IOM I 1 0R A MAxLMUM MOOT 0PM MSU=l6 (I 048 5T6 T WORDS) PER sYsTEM TOM OR CPM Fig. 2A

PATENIEUSEP 9I975 S05 1 02? SIZE" 6 L IPROGRAM SECTION TEXECUTION SECTION M I I FAULT A8 I CONTROL k I I LOGIC I I I ADDRESS I COMPUTATION I I I UNIT I I I 54 62 I l PROGRAM EXECUTION l CONTROL I UNIT EXECUT'ON I I UNIT I QUEUES I k i I 56 I I M I I I I I I PROGRAM BARREL I IIII I I ALIGNMENT I QUEUES SELECT I I I I /48I I 52 50 I I ODD EVEN IQ; STORAGE ASSOCIATWE STACK A l I PROGRAM PROGRAM T BUFFER BUFFER I I BUFFER BUFFER I I (ASM) I I I A I I I I F I I I COMMUNICATIONS I I UNIT I I STORAGE SECTION I J MAIM MEMORY Fig.4

PATENTEU 9175 3805,0213

l M 10 MEMORY I TOP OF STACK I II LOCATIONS I Fig.5 f A i I l I B l WORD HYX STACK AREA 6 ASSIGNED YOs wow 5 5 T0 PROORAM STACK AREA E |STAGK LIMIT REGISTER I CURRENTLY T YMOsE LOSR 6? I l 1 W0 A i BOSR 65 l STACK MEMORY AREA PROGRAM BUFFER STACK BUFFER 48 ASSOCIATIVE MEMORY 52 MSCW 2 MSW PROCESSOR MAYM MEMORY STACK AREA PROGRAM Q AREA MSQW- Mscw Mscw MSCW PATENTED 55F 9 975 TOP UF smgggcmnows Fig.6 A -1 B INPUT/OUTPUT PATH OF DATA TO/FROM STACK I Fos WORD STACK COPY NOT IN CORE BUFFER AREA -I CURRENTLY [MUSE COPYINOORE I I STACK 50/ BUFFER REGISTERSLINKING J CORRESPONDING POINTS IN STACK BUFFER Fig.7

STACK BUFFER 50 FOUR WORD SEGMENT TPP NEWENTRIES BTP BEI EANIIEIF SAR}SAR 0R SLR OSLR ISTOBEUSED AS BASE LEGEND FOR REGISTERS BTP-OLDEST STACK BUFFER ENTRY TPP-NEWEST STACK BUFFER ENTRY S LAST RESERVED MEMORY STACK ADDRESS STACK MEMORY AREA LOSR S REC.

CURRENTLY BOSR MEMORY STACK AREA SUR SAR

INCREASING ADDRESSES SLR-MEMORY ADDRESS OF OLDEST STACK WORD FOR WHICH THERE IS NO COPY SAR-MEMORY ADDRESS OF OLDEST STACK ENTRY RESIDENT IN THE STACK BUFFER PMENFHLSEP 1975 995 023 CONTROLS STACK BUFFER su PB TOREOuEsTOR REQiJEST REOJOEsT REQTEST PRIORITY OONTROL cu RENENBER-sOsPENO HMNG REcElvERs- REGISTER AND DRIVERS OONTROL STACK TOO sOR OONTROLs CONTROLS MEMORY l l 1 T OONTROLs COMMUNICATIONS FAIL FAULT SIGNALS ADDRESS REGISTER REGISTER TRON OPM NW5 1 306 30KB FROM OONNONTOATTONO PARITY LENGTH REOTsTER REQUESTORQ CHECK GENERATE sTRON BUFFER su DATA QUOTE-- INPUT REGISTER OOTPOT REOTsTER l l L 302 TO TOWN TO sTRON AND ASM PROGRAM BUFFER BUFFER 48 REOELvERs- DRIVERS MEMORY Fig. 9

PATENTEDSEF 9I975 2.905023 SHEET 1D 26 2524 23 22 2| 2O I9 I8 IT I6 I5 I4 I?) I2 II IO 9 4 3 O (O IINEEEP AIIIICIS NPUUUE DCNRCN MADS BN R I C R P R D N P S E A W QM V A V EU-OZ PCU-56 COMM MEMORY INTERNAL INTERNAL INTERNAL RELATED ERRORS ERRORS ERRORS ERRORS FIELD BITS DESCRIPTION INR 26=I INHIBIT NORMAL RETURN WPI 25=I WRONG PIRIPIR MAY BE ONE LESS) EUC 24=I EU CONTINUITY ERROR EUR 25=I EU RESIDUE ERROR EUP 22=I EU PARITY ERROR PER 2| =I PCU ERROR 20=I NOT USED ADD I9=I RESIDUE ERROR IN ADDER WCN I8 =I WRONG CHANNEL NUMBER INP IT=I COMM. UNIT RECEIVED BAD PARITY' FROM STACK BUFFER OR STACK DATA OUEUE CRS I6=I COMM. UNIT RESIDUE ERROR ICE I5=I ERROR OCCURREDON OPERATION THAT WAS IGNORED SNA I4=I COMM. UNIT DID NOT RECEIVE A REOUESTOR OPERATION COMPLETE SIGNAL FROM MCM F2 I3=| SINGLE BIT ERROR SU I2=I O NOT SU OPERATION I SU OPERATION SK II=I O= NOT STACK OPERATION I STACK OPERATION OP IO=I O= FETCH I-= STORE MADS 9=6 MEMORY ADDRESS BN 3=4 BOX NUMBERIMCH NO.)

PATENTEUSEP 9W5 3,905,023

sum 13 INPUT/OUTPUT mooum 82 DFI 2M BYTES/SEC. 4 CHANNELS DF PCC"I 22.9% MEM. PORT 2WD x 2 W0 I6M BITS/SEC.

BUFFER/CHAN.

a2 DFI 2M BYTES/SEC. 4 CHANNELS DF Pm 22.9% MEM. PORT z wgg z gg 16M BITS/SEC. 615M BYTES/SEC.

mo /0mm PORT A0 POI 2M BYTES/SEC. 596%MEM.PORT ,EE IGMBITS/SEC. at

0.75M BYTES/SEC. DCP-DCI DCP |-4 14.6% MEM. PORT 1WD BUFFER/\NTERF. 6M BITS/SEC.

Fig/4 BASE ADDRESS(BA) BA+2 BA+4 BA+5 BUFFER DESCRIPTOR 1/0 D LINKAGE SIDEUNK AREA 100w con 10R (NU BASE ADDRESS WORDO WORDI WORDE worm WORD4 worms worms 6 THRU N ARE RESERVED FOR SOFTWARE USE ONLY F lg. 2/

PATENTEEISER RARE 9.905.023

saw 14 QUEUE OF 324 FIG.|5A FIGISB FAILIOCB'SUO) NL NOT USED QB NL NOTUSED QB i NOTESI FAIL I. DERIVED FROM HA WORD 3 NOTUSED RD 2. BD,IOCW,ANDCDLWORDSNOTSHOWN 5. NULL(0)PRIOR TOSlDELlNK-,SIDELINK M m ADDRESS AFTER SIDELINK (NULL) NOT USED RD 4. DASHED LINES INDICATE POlNTERS AFTER SIDELINK P/O 1/0 QUEUE P/O 1/0 ouEuE (DEVICE 25410083) (DEVlCE l 1005's) SL SL ML (0) NOTE2 RD NL (0) NOTE2 RD NL SL SL (N075) 0 NOTEZ RD NL (01 NOTEZ RD FJ SL NOTE2 RD NL 8L A0TE2 RD I NL SL I (m (0) NOTEZ RD I STATUS ouEuE P |0M(n) PORTION NL NOTE2 RD l 5L TERMINATED NL NOTE 2 RD IOCBS ALL (0) DEVICES .L

{*6 NOTEZ RD iq- PATENTEUSEP 9l975 3,905,023

IOM (n) LEVEL-l MEMORY HOME ADDRESS WORD STORED SELECT UT UN'HABLE flm HOME ADDRESS (000) WORD 0 m W0 UT WD,DEVICE I TiEKEREED S SELECT UT H ADD (NOTE I) WORD UT WD,DEVICE 255 51a STORED GS HE JH B EH SELECT U0 QUEHJIELHIESQHTQJBDLE TABLE ADDRESS (000) WORD 0 IOQH WORD DEVICE! ADD UD STORED so NUMBER s gkg f: HEADER ADDRESS (NOTE I) n IOQH WORD DEVICE 254 IOQH WORD DEVICE 255 D SELECT M 1/0 QUEUE TAILTABLE 3 g WORM V FAILIOQTWD 100T WORD DEVICEI SELECT IOQT WORD n 100T WORD DEVICE 254 IOOTWORD DEVICE 255 IOM(H)STATUS 322 QUEUEHEADER HEAD TAIL FIELD FIELD Fig. /5A

PATENTEUSEF 9W5 3,905,023

sum 17 P A f TAG (SOFTWARE USE ONLY) ADDRESSOF FIRST 1008 T Y Fig/6 P A f TAG (SOFTWARE USEONLY) ADDRESS OF FIRST 1005 T Y IF; L 5 g N R TAG 0 A A 0PM U E HEADFIELD TAILFIELD I c R N NUMBER L 1 Y E 5| 50 4s 41 4e 45 44 42 4| 4o 59 mm (STANDARD comm HELD) P A ALSIBIATFMBETAG l TAG s K A R M P s on (NOTUSED) c A L T N T Y 51 so 48 4? 46 45 44 45 42 4| 40 39 5a 54 3e 55 Fig. 22

PATENTEUSEP 91975 3.905.023

SHEE? 1a PERIPHERAL |()P(;(;

8MCM W (PCI) (MIU) W H FILE INTERFACE (DFI) PE? INTERFACE (DFI) CPMI TRANSLATOR SCAN BUS /T6 INTERFACE 2DFO DCP MEMORY |INTERFAGEI '4DCP (D01) 78 INPUT/OUTPUT MODULE DATA XFER 4 SUBSECTION BATCH DATAAND MEMORY EQQEE CONTROL INTERFACE DATA SUBSECTION DATA AND (LEVEL IMEMORY (MIU) I HIGH CONTROL SPEED TO/FROM CONTROL UP T0225 RRR O CENTRAL IINTERRUPTS CONTROL COMMUNWONS MEMORY) $88? (TRANSLATOR) REAL-TIME INTERACTIVE 72 Fig. 24

IOM DATA TRANSFER SUBSECTIONS PATENTEUSEP 9|975 3.905023 Sl-iEEI T9 RATCII IIIIIEPRIIITER LINEPRINTER CDIITRDIIIPC) (LP) CARD PUNCH UNIT CARD PIIIICII CCIITRDIIPIICI UNIT(PU) F1 25 CARD READER CARD READER CCIITRCIICRCI ICRI SINGLE LINE H oPERAToRs CONSOLE CCIITRCIIsLCI A DISPLAYISPO) IIIACIIETIC TAPE I IACIIETIC TAPE CCIITRCIIIITCI DRITIIIITIII PAPER TAPE PIIIIICII E PAPER TAPE CDIITRDLIPTPCI PIIIICIIIPTPI PAPER TAPE READER PAPER TAPE CONTROUPTRC) READERIPTRI II PERIPHERAL CCIITRCIIPCI BUS SCAN Dus IIICII SPEED 80 DISK PACK DRIvE DIsII PACK A' YP CONTROLLER(PTRC) DRIITEIDPDI IIITERTACE (PCT) (20 MAX) DIsII FILE a2 CDIITRDIIDECI DISK FACE EEW 'ICIIIAXI DISKFILE DISK FILE 4 ELECTRONICS H STORAGEUNIT /Y6 IIIIITIDEEIII IDTsID sCAII H TCII INTERFACE W (5CD REAL TIME IIITERACTIIIE DATA DIsII FILE CCIIIIDIIICATIDIIs II OPT'M'ZERWFO) INTERFACE M m) (4 AX) I DATA COMMUNICATIONS DATA CDIIII.

PRDCECCDRIDCPI TCD 

1. A multi-processing modular data processing system including a plurality of peripheral devices comprising: a plurality of memory modules interconnected by a memory bus to provide a multi-accessable main memory for said system, each of said plurality of memory modules including a memory control unit and at least one memory storage unit, each of said memory control units being connected to said memory bus and including means for detecting errors in the transfer of information between said memory bus and said memory storage unit; a plurality of central processing modules, each of said plurality of central processing modules including a program control section and a storage section, each of said storage sections being connected to said memory bus and including means for indicating malfunctions internal to said respective processing module and errors related to information transfer between said respective processing module and said main memory; a plurality of input/output modules, each of said input/output modules including a memory interface unit and a translator unit, said memory interface unit of each of said plurality of input/output modules being connected to said memory bus, said translator unit of each of said plurality of input/output modules being connected to said program control section of each of said processing modules for receiving control information and including means for detecting and reporting malfunctions internal to said respective input/output module and errors related to information transfers between said respective input/output module and said plurality of peripheral devices; a maintenance bus coupled to each of said memory control units of said plurality of memory modules and to each of said storage sections of said plurality of central processing modules and to each of said memory interface units of said plurality of input/output modules; and maintenance diagnostic means coupled to said maintenance bus for off-line testing of each of said plurality of said central processing modules, each of said plurality of input/output modules, and said memory control units of each of said plurality of memory modules;
 2. The data processing system of claim 1 wherein said memory control unit further includes: means for correcting all single-bit errors in information received from said at least one memory storage unit associated with said memory control unit before said transfer of information to said memory bus. 